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NVIDIA has presented AutoDMP – a new methodology that combines GPU-accelerated computing with AI to improve chip design and increase semiconductor performance and efficiency.
The solution is developed to address the issue of macro placement, which impacts power-performance-area (PPA) metrics. AutoDMP "places macros and standard cells concurrently in conjunction with automated parameter tuning using a multi-objective hyperparameter optimization technique", allowing the company to generate high-quality predictable solutions and improve the macro placement quality of academic benchmarks.
NVIDIA also says that AutoDMP is computationally efficient, "optimizing a design with 2.7 million cells and 320 macros in 3 hours on a single NVIDIA DGX Station A100."
Here is how the company describes AutoDMP's PPA evaluation:
"First, the AutoDMP multi-objective parameter optimization finds a set of placements whose estimated wire length, congestion, and density lie on the Pareto front. This step essentially maps the design space of the AutoDMP parameters to the objective proxy space.
Then, map the macro placements on the objective space Pareto front to the EDA tool’s real PPA space. The two Pareto fronts likely will not match since the EDA tool conducts numerous optimizations of the placement, many of which are heuristic-driven and therefore very difficult to predict.
Consequently, run the EDA tool on all the macro placements from the Pareto front of the objective proxy space and evaluate real PPA metrics, such as routed wire length, timing, and power obtained from the EDA tool flow execution."
According to NVIDIA's blog post, AutoDMP's PPA metrics are equal to or better than the commercial flow. The company notes its effectiveness in combining GPU-accelerated placers with AI/ML multi-objective parameter optimization and hopes this methodology can unlock new prospective design space exploration techniques.
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